A multi-threshold complementary metal-oxide semiconductor technology (MTCMOS technology) is employed in the field of integrated circuits for reducing a leakage current and/or for improving an operating speed. In a chip, the operation speed of particular circuit elements can be increased by realizing related transistors with low threshold voltages. Similarly, by implementing some circuit elements with transistors having a high threshold voltage, the leakage current of the circuit elements in a non-conducting state is reduced.
However, employing the MTCMOS technology in an integrated circuit always results in a trade-off between operation speed and leakage current. For instance, when increasing the threshold voltage of a transistor (resulting in a reduced leakage current), the operating speed of the transistor decreases, limiting the circuit performance. A similar trade-off also applies for transistors with a low threshold voltage causing the problem of a higher leakage current.
A different approach for reducing the leakage current teaches to cut off circuit elements from the power supply when they are not needed. However, a cut off power supply will result in a loss of information on an internal operating state. In particular, memory elements such as latches, flip-flops and other storage circuit elements depend on externally supplied power as the internal operational state can only be retained with an always-on power supply. Accordingly, in many circuit elements, state retention is necessary for recovering a circuit operation after a period with a cut off power supply.
Mobile devices depend heavily on an efficient use of the supplied power. Nevertheless, a reduction of leakage current is not limited to mobile devices. General purpose integrated circuits may also benefit from reduced leakage currents. The reduction of leakage currents becomes more important for integrated circuits of reduced size process technologies. Due to reduced transistor geometry, the amount of leakage currents increases and existing power reduction techniques are difficult to apply. In this respect, the MTCMOS technology may be employed in integrated circuits with decreased power consumption, for instance, in integrated circuits which are designed for portable uses, such as laptop computers, mobile phones, GPS, PDA, smart phones, MP3 players and the like. In particular, mobile devices are typically kept in an idle or a deep sleep mode for a considerable amount of time, consuming only leakage power.
An example of a master slave flip-flop circuit employing the MTCMOS technology is disclosed in U.S. Pat. No. 6,870,412 B2. In particular, this document discloses a master slave flip-flop circuit connected to a retention circuit. For reducing the power consumption in a sleep mode, inverter elements affecting the operational speed are implemented using transistors with a low threshold voltage. Additionally, said transistors are connected to a virtual ground terminal, which can be disconnected from ground potential for preventing a leakage current from flowing to ground in a sleep state. Further, the data from the flip-flop can be retained in the retention circuit. Circuit elements connecting the retention circuit comprise high-threshold voltage transistor, which prevents leakage currents in the sleep mode.
Another example of a master slave flip-flop circuit employing the MTCMOS technology is disclosed in “A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits” by Shigematsu, Satoshi et. al. IEEE Journal of Solid-State Circuits, Vol. 32, No. 6, June 1997. For reducing the power consumption in sleep mode, the transistors of the master slave flip-flop are implemented as low-threshold voltage transistors connected to a virtual ground line. By disconnecting the virtual ground line from ground potential, the leakage current of transistors included in the master slave flip-flop circuit can be reduced. Moreover, a first retention circuit for the state of the master slave flip-flop and a second retention circuit for the clock signal are provided allowing the recovery of the operational state. The circuit elements of the retention circuits are realized using transistors with a low threshold voltage.
A further example of a master slave flip-flop circuit implemented using the MTCMOS technology is disclosed in U.S. Pat. No. 7,138,842 B2. The disclosed circuit has a master slave latch structure further comprising a retention latch connected for receiving data from the slave latch and for inputting data to the master latch. In particular, the master and slave latch includes inverters that can be disconnected from the power supply. Further, the inverters of the retention latch are realized as low-leakage devices, namely transistors with a high threshold voltage whereas the inverters included in the master slave flip-flop use low threshold voltage transistors.
An example of an integrated circuit comprising a master latch and a slave latch using the MTCMOS technology is disclosed in WO 2006/127888 A2. In normal operation mode, data from the master latch is input and stored in the slave latch. In the standby mode, the master latch is cut off from the power supply, whereas the slave latch continues to receive power in order to retain the input data. In order to decrease the leakage current, the implementation of the transistors in the integrated circuit realizes the transistors in two active regions in the silicon substrate, a first active region having a first type ion implantation and a second active region having a second type ion implantation.
Another example of a master slave flip-flop integrated circuit employing the MTCMOS technology is disclosed in US 2009/0066386 A1. In the disclosed master slave flip flop structure, the master latch and the slave latch are connected to different grounds. In particular, the slave latch is connected to real ground, whereas the master latch is connected to a virtual ground which can be disconnected by a high-threshold voltage transistor from ground potential. All other switching elements are provided as low-threshold voltage transistors.
An example of a master slave flip-flop integrated circuit employing the MTCMOS technology is disclosed in US 2010/0001774 A1. The disclosed master slave flip-flop structure comprises a master latch which also realizes as a retention circuit. In particular, the retention circuit in the master latch is implemented using high-threshold voltage transistors, whereas the master latch further comprises low-threshold voltage transistors. The slave latch is implemented using low-threshold voltage transistors. In a sleep mode, the power supply is cut off from all circuit elements except for the circuit elements forming the retention circuit. Accordingly, the leakage current can be reduced in the sleep mode.
All of the described integrated circuits focus on a reduction of leakage currents in a sleep mode. However, power losses are not only a problem in a sleep mode but also occur during operation and are called dynamic power losses. Specifically, when changing an operating state in a master slave flip-flop, the switching operation triggered by a clocking pulse results in a switching current, which is usually referred to as dynamic power consumption.
Consequently, one of the main problems concerning the above described master slave flip-flop integrated circuits relates to the dynamic power consumption of flip-flop circuits. In particular, the MTCMOS technology is employed for reducing leakage current in a sleep mode by preventing leaking current in circuit elements operating in the sleep state but does not contribute towards a reduced power consumption in the operating state.
An example for reducing the power consumption of CMOS latches and of flip-flops is disclosed by “New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power savings”, Yuan, Jiren and Svensson, Christer, IEEE Journal of Solid-State Circuits, Vol. 21, No. 1, January 1997. In order to face the demands for high speed and low power consumption, static differential latches and static flip-flops are disclosed, minimizing the clock load by reducing the number of clocked transistors. In particular, a static ratio-insensitive differential p-latch and a static ratio-insensitive differential n-latch are disclosed, which are provided with only a single clock signal. However, the static ratio-insensitive differential n-latch is slower than other static differential n-latches. Accordingly, the disclosed static flip-flops combine, for instance, the static ratio-insensitive differential p-latch with faster static differential n-latches rather than a static ratio-insensitive differential n-latch in order to achieve an improved operating speed.
Given these problems with the existing technology, it would be advantageous to provide an integrated circuit that provides a master slave flip-flop circuit employing the MTCMOS technology also reducing its dynamic power consumption in the operating state.